Field
The present technique relates to the field of data processing systems. More particularly, it relates to the control of thread issue into a processing pipeline within a data processing system.
Description
It is known to provide data processing systems having processing pipelines which can execute a plurality of threads in parallel. As an example, the threads may correspond to different fragments of an image to be generated within a graphics processing system. The use of deep pipelines supporting multiple threads in parallel execution enables a high level of data throughput to be achieved.
One problem associated with such systems is the latency associated with fetching from main memory data required to be accessed during processing. It is known to provide cache memories close to the processing pipeline in order to provide rapid and low energy access to data to be processed. However, data needs to be moved between the cache memory and the main memory as the cache memory has insufficient capacity to hold all of the data which may be required. When a thread makes an access to a data value which is not held within the cache memory, then a cache miss arises and the cache line containing that data value is fetched from the main memory. The time taken to service such a cache miss may be many hundreds of clock cycles and the thread which triggered the cache miss is stalled (parked) during such a miss until the required data is returned. It is known to provide data processing pipelines with the ability to manage stored threads in this way and still make forward progress with threads which are not stalled.
In order that the system should operate efficiently, it is desirable that the capacity to deal with stalled threads should not be exceeded. Conversely, the overhead associated with managing stalled threads is not insignificant and accordingly it is undesirable to provide an excess of this capacity. Furthermore, it is desirable that not too much of the processing capabilities of the processing pipeline should be stalled at any given time as a consequence of threads awaiting data for which a cache miss has occurred.